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document number: mc33990 rev 3.0, 11/2006 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2006. all rights reserved. enhanced class b serial transceiver the 33990 is a serial transceiver designed to provide bi-directional half-duplex comm unication meeting the au tomotive sae standard j- 1850 class b data communication network interface specification. it is designed to interface directly to on-board vehicle microcontrollers and serves to transmit and receive data on a single-wire bus at data rates of 10.4 kbps using variable pulse width modulation (vpwm). the 33990 operates directly from a vehicle's 12 v battery system and functions in a true logic fashion as an i/o interface between the microcontroller's 5.0 v cmos logic level swings and the required 0 v to 7.0 v waveshaped signal swings of the bus. the bus output driver is short circuit current limited. features ? designed for sae j-1850 class b data rates ? full operational bus dynamics over a supply voltage of 9.0 v to 16 v ? ambient operating temperature of -40 c to 125 c ? interfaces directly to standard 5.0 v cmos microcontroller ? bus pin protected against shorts to battery and ground ? thermal shutdown with hysteresis ? voltage waveshaping of bus output driver ? internally reverse battery protected ?40 v max v bat capability ? pb-free packaging designated by suffix code ef figure 1. 33990 simplified application diagram j-1850 serial transceiver d suffix ef suffix (pb-free) 98asb42564b 8-pin soicn 33990 ordering information device temperature range (t a ) package mc33990d/dr2 -40c to 125c 8 soicnn MCZ33990EF/r2 bus +vbat sleep tx rx 4x/loop gnd load primary node mcu v bat secondary nodes 33990
analog integrated circuit device data 2 freescale semiconductor 33990 internal block diagram internal block diagram figure 2. 33990 simplified internal block diagram 33990 voltage regulator bus driver thermal shutdown waveshaping filter bus 4.5 v reference vbat sleep tx rx 4x/loop 4x enable loopback digital output driver loss of ground protection gnd load note this device contains approximately 400 active transistors and 250 gates.
analog integrated circuit device data freescale semiconductor 3 33990 pin connections pin connections figure 3. 33990 pin connections table 1. 33990 pin definitions pin number pin name definition 1 sleep enables the transceiver when logic 1 and disables the transceiver when logic 0. 2 gnd device ground pin. 3 load accommodates an external pull-down resistor to ground to provide loss of ground protection. 4 bus waveshaped sae standard j-1 850 class b transmitter ou tput and receiver input. 5 v bat provides device operating input power. 6 4x/ loop tristate input mode control; lo gic 0 = normal waveshaping, logic 1 = waveshaping disabled for 4x transmitting, high impedance = loopback mode. 7 tx serial data input (di) from the microcontroller to be transmitted onto bus. 8 rx bus received serial data output (do) sent to the microcontroller. 2 3 4 8 7 6 5 1 1 2 4 3 8 7 5 6 rx tx v bat 4x/loop sleep gnd load bus
analog integrated circuit device data 4 freescale semiconductor 33990 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit v bat dc supply voltage (1) v bat -16 to 40 v input i/o pins (2) v i/o(cpu) -0.3 to 7.0 v bus and load outputs v bus -2.0 to 16 v esd voltage human body model (3) machine model (4) v esd1 v esd2 2000 200 v storage temperature t stg -65 to 150 c operating ambient temperature t a -40 to 125 c operating junction temperature t j -40 to 150 c peak package reflow temperature during reflow (5) , (6) t pprt note 6. c thermal resistance (junction-to-ambient) r j-a 180 c / w notes 1. an external series diode must be used to provide reverse battery protection of the device. 2. sleep , tx, rx, and 4x / loop are normally connected to a microcontroller. 3. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 4. esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 5. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability meet s pb-free requiremen ts for jedec standard j-std-020 c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale .com, search by part number [e.g. remove pr efixes/suffixes and ente r the core id to view all ordera ble parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data freescale semiconductor 5 33990 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electrical characteristics characteristics noted under conditions of 7.0 v v bat 16 v, -40 c t a 125 c, sleep = 5.0 v unless otherwise noted. typical values reflect the parameter's approximate midpoint average value with v bat = 13 v, t a = 25c. all positive currents are into the pin. all negative currents are out of the pin. characteristic symbol min typ max unit power consumption operational battery current (rms with tx = 7.812 khz square wave) bus load = 1380 ? to gnd, 3.6 nf to gnd bus load = 257 ? to gnd, 20.2 nf to gnd i bat (op1) i bat (op2) ? ? 3.0 22.4 11.5 32 ma battery bus low input current after sleep toggle low to high; prior to tx toggling after tx toggle high to low i bat(bus l1) i bat(bus l2) ? ? 1.1 6.4 3.0 8.5 ma sleep state battery current v sleep = 0 v i bat(sleep) ? 38.2 65 a bus bus input receiver threshold (7) threshold high (bus increasing until rx 3.0 v) threshold low (bus decreasing until rx 3.0 v) threshold in sleep state ( sleep = 0 v) hysteresis (v bus(ih) - v bus(il) , sleep = 0 v) v bus(ih) v bus(il) bus th(sleep) v bus(hyst) 4.25 ? 2.4 0.1 3.9 3.7 3.0 0.2 ? 3.5 3.4 0.6 v bus -out voltage (tx = 5.0 v, 257 ? r bus(l) to gnd 1380 ? ) 8.2 v v bat 16 v 4.25 v v bat 8.2 v tx = 0 v v bus (out1) v bus (out2) v bus (out3) 6.25 v bat - 1.6 ? 6.9 ? 0.27 8.0 v bat 0.7 v bus short circuit output current tx = 5.0 v, -2.0 v v bus 4.8 v i bus (short) 60 129 170 ma bus leakage current -2.0 v v bus 0 v ( 2.0 ms after tx falls to 0 v) 0 v v bus v bat 0 v v bus 8.0 v i bus (leak1) i bus (leak2) i bus (leak3) -0.5 -0.5 ? -0.055 0.5 0.25 0.5 1.0 0.5 ma bus thermal shutdown (8) (tx = 5.0 v, i bus = -0.1 ma) increase temperature until v bus 2.5 v t bus (lim) 150 170 190 c bus thermal shutdown hysteresis (9) t bus (lim) - t bus (reen) t bus (li mhys) 10 12 15 c load input current with loss of ground v load = -18 v (see figure 4 ) i load (log) -1.0 ? 0.1 ma bus input current with loss of ground v bus = -18 v (see figure 4 ) i bus (log) -1.0 ? 0.1 ma notes 7. typical threshold value is the approximate actual occurring switch point value with v bat = 13 v, t a = 25c. 8. device characterized but not production tested for thermal shutdown. 9. device characterized but not production tested for thermal shutdown hysteresis.
analog integrated circuit device data 6 freescale semiconductor 33990 electrical characteristics static electrical characteristics table 4. static electrical characteristics (continued) characteristics noted under conditions of 7.0 v v bat 16 v, -40 c t a 125 c, sleep = 5.0 v unless otherwise noted. typical values reflect the parameter's approximate midpoint average value with v bat = 13 v, t a = 25c. all positive currents are into the pin. all negative currents are out of the pin. characteristic symbol min typ max unit bus (continued) bus input current with loss of v bat v bus = 9.0 v (see figure 5 ) i bus (lob) ? ? 0.5 ma load output i l = 6.0 ma l on ? 0.07 0.2 v unpowered load output v bat = 0 v, i l = 6.0 ma l dio 0.3 0.67 0.9 v tx tx input voltage v bus 3.875 v v bus 3.875 v v tx(il) v tx(ih) ? 3.5 2.27 2.27 0.8 ? v tx input current v tx = 5.0 v v tx = 0 v i tx(ih) i tx(il) 50 -2.0 120 -0.1 200 2.0 a loop 4x / loop input current v 4x / loop = 0 v (normal mode) v 4x / loop = 5.0 v (4x mode) i 4x / loop(il) i 4x / loop(ih) -200 ? -95 95 ? 200 a 4x / loop input threshold (tx = 4096 hz square wave) normal mode to loopback mode loopback mode to 4x mode v 4x / loop(il) v 4x / loop(ih) 1.4 3.2 1.6 3.43 1.8 3.6 v rx rx output voltage low v bus = 0 v, i rx = 1.6 ma v rx (low) 0.01 0.18 0.4 v rx output voltage high v bus = 7.0 v, i rx = -200 a v rx(high) 4.25 4.48 4.75 v rx output current v r x = high; short circuit protection limits i rx 2.0 5.9 8.0 ma rx sleep state output voltage sleep = 0 v, 0 v bus 7.0 v v rx 4.25 4.56 4.85 v sleep input current v sleep = 0 v v sleep = 5.0 v i sleep (il) i sleep (ih) ? 1.0 -0.003 9.5 -2.0 20 a
analog integrated circuit device data freescale semiconductor 7 33990 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electrical characteristics characteristics noted under conditions of 7.0 v v bat 16 v, -40 c t a 125 c, sleep = 5.0 v unless otherwise noted. typical values reflect the parameter's approximate midpoint average value with v bat = 13 v, t a = 25c. all positive currents are into the pin. all negative currents are out of the pin. characteristic symbol min typ max unit bus bus voltage rise time (10) (9.0 v v bat 16 v, tx = 7.812 khz square wave) (see figure 6 ) bus load = 3,300 pf and 1.38 k ? to gnd bus load = 16,500 pf and 300 ? to gnd t rise (bus) 9.0 9.0 11.15 11.86 15 15 s bus voltage fall time (10) (9.0 v v bat 16 v, tx = 7.812 khz square wave) (see figure 6 ) bus load = 3,300 pf and 1.38 k ? to gnd bus load = 16,500 pf and 300 ? to gnd t fall (bus) 9.0 9.0 10.50 11.17 15 15 s pulse width distortion time (9.0 v v bat 16 v, tx = 7.812 khz square wave) (see figure 7 ) bus load = 3,300 pf and 1.38 k ? to gnd t pwd (bus) 35 62 93 s propagation delay tx threshold to rx threshold t pd (bus) ? 17.7 25 s tx tx to bus delay time (tx = 2.5 v to v bus = 3.875 v) ( figure 8 ) 4x mode normal mode t txdelay ? 13 2.6 17.3 4.0 24 s sleep to tx setup time ( figure 8 ) t sleeptxsu 80 40 ? s rx rx output delay time (tx = 2.5 v to v bus = 3.875 v) (see figure 9 ) low-to-output high high-to-output low t rxdelay / l?h t rxdelay / h?l ? ? 0.11 0.38 2.0 2.0 s rx output transition time (c rx = 50 pf to gnd, 10% and 90% points) (see figure 10 ) low-to-output high high-to-output low t rxtrans / l?h t rxtrans /h?l ? ? 0.34 0.08 1.0 1.0 s rx output transition time (11) (c rx = 50 pf to gnd, sleep = 0 v, 10% and 90% points) (see figure 10 ) low-to-output high high-to-output low t rxtrans / l?h t rxtrans /h?l ? ? 0.32 0.08 5.0 5.0 s notes 10. typical is the parameter's approximate average value with v bat = 13 v, t a = 25c. 11. rx output transition time from a sleep state.
analog integrated circuit device data 8 freescale semiconductor 33990 electrical characteristics electrical performance curves electrical performance curves test figures figure 4. loss of ground test circuit figure 5. loss of v bat test circuit figure 6. bus rise and fall times figure 7. pulse width distortion figure 8. sleep to tx delay times figure 9. bus-to-rx delay time i load (log) i bus (log) 33990 v bat gnd bus load floating -18 v 9.0 v i bus (lob) vbat gnd bus floating 33990 64 s 3.5 v 0.8 v tx 80% 20% bus t rise t fall 64 s 5.0 v 0 v tx 1.5 v t pwd(max) t pwd t pwd(min) bus sleep 2.5 v t sleep txsu tx 2.5 v 3.875 v t txdelay rx 2.5 v bus t rxdelay / low- to-output high 122 s 3.875 v t rxdelay /high-to- output low
analog integrated circuit device data freescale semiconductor 9 33990 electrical characteristics test figures figure 10. rx rise and fall time t rxtrans / l?h t rxtrans / h?l 90% 10% 90% 10% rx
analog integrated circuit device data 10 freescale semiconductor 33990 functional description introduction functional description introduction the 33990 is a serial transceiver device designed to meet the sae standard j-1850 class b performance for bi- directional half-duplex communication. the device is packaged in an economical surface-mount soic plastic package. an internal block diagram of the device is shown in figure 2 . the 33990 derives its robustness to temperature and voltage extremes from being built on a smartmos process, incorporating cmos logic, bipolar/mos analog circuitry, and dmos power fets. though the 33990 was principally designed for automotive applications requiring sae j-1850 class b standards, it is suited for other serial communication applications. it is parametrically specified over an ambient temperature range of -40 c t a 125 c and 7.0 v v bat 16 v supply. the economical 8-pin soicn surface mount plastic package makes the device a cost-effective solution. functional pin description input power (vbat pin) this is the only required input power source necessary to operate the 33990 . the internal voltage reference of the 33990 will remain fully operational with a minimum of 9.0 v on this pin. bus transmissions can continue with battery voltages down to 5.0 v. the bus output voltage will follow the battery voltage down and, in doing so, track approximately 1.6 v below the battery voltage. the device will continue to receive and transmit bus data to the microcontroller with battery voltages as low as 4.25 v. the pin can withstand voltages from -16 v to 40 v. sleep input ( sleep pin) this input is used to enable and disable the class b transmitter. the class b receiver is always enabled so long as adequate v bat pin voltage is applied. when the sleep pin voltage is 5.0 v, the class b transmitter is enabled. if this input is logic low, the class b transmitter will be disabled and less than 65 a of current will be drawn by the v bat pin. the pin also provides a 5.0 v reference, internal to the device, used to establish the rx output level and slew rate times. class b functional description the transmitter provides an analog waveshaped 0 v to 7.0 v waveform on the bus output. it also receives waveforms and transmits a digital level signal back to a logic ic. the transmitter can drive up to 32 secondary class b transceivers (see figures 11 and 12 ). these secondary nodes may be at ground potentials that are 2.0 v relative to the control assembly. waveshaping will only be maintained during 2 of the 4 corners when the 0 to 2.0 v ground potential difference condition exists. the 33990 is a secondary node on the class b bus. each secondary transceiver has a 470 10% pf capacitor on its output for emi suppression purposes, as well as a 10.6 k ? 5% pull- down resistor to ground. the primary node has a 3300 10% pf capacitor on its output for emi suppression, as well as a 1.5 k ? 5% pull-down resistor to ground. with more than 26 nodes, there is no primary node (see figure 13 ). all nodes will have a 470 10% pf capacitor and a 10.6 k ? 5% pull- down resistor. no matter how many secondary nodes are on the class b bus, the rc time constant of the class b bus is maintained at approximately 5.0 s. the minimum and maximum capacitance and resistance on the class b bus is given by the expressions shown in table 6 . figure 11. minimum bus load figure 12. maximum number of nodes 3300 pf 1.5 k ? 470 pf 10.6 k ? one primary node 1.5 k ? 470 pf 10.6 k ? primary node 442 ? 24 secondary nodes 3300 pf 11280 pf
analog integrated circuit device data freescale semiconductor 11 33990 functional description functional pin description figure 13. maximum bus load 14570 pf 342 ? 470 pf 10.6 k ? 31 secondary nodes table 6. class b bus capacitance and resistance expressions level capacitance resistance to ground minimum (3.3 x 0.9) + (0.47 x 0.9) = 3.39 nf (1.5 x 0.95) || (10.6 x 0.95) / 25 = 314 ? maximum (3.3 x 1.1) + 25 (0.47 x 1.1) = 16.55 nf (1.5 x 1.05) || (10.6 x 1.05) = 1.38 k ?
analog integrated circuit device data 12 freescale semiconductor 33990 typical applications functional pin description typical applications class b module inputs transmitter data from the mcu (tx) the tx input is a push-pull (n-channel / p-channel fets) buffer with hysteresis for noise immunity purposes. this pin is a 5.0 v cmos logic level input from the mcu following a true logic protocol. a logic [0] input drives the bus output to 0 v (via the external pull-down resistor to ground on each node), while a logic [1] input produces a high voltage at the bus output. a logic [0] input level is guaranteed when the tx input pin is an open-circuit by virtue of an internal 40 k ? pull-down resistor. no external resistor is required for its operation. waveshaping and 4x / loop this input is a tristateable input: 0 v = normal waveshaping, 5.0 v = waveshaping is disabled for 4x transmitting, and high impedance = loopback mode of operation. this is a logic level input used to select whether waveshaping for the class b output is enabled or disabled. a logic [0] enables waveshaping, while a logic [1] disables waveshaping. in the 4x mode, the bus output rise time is less than 2.0 s and the fall time is less than 5.0 s (owing to the external rc pull-down to ground). in the loopback condition, the tx signal is fed back to the rx output after waveshaping without being transmitted onto the bus. this mode of operation is useful for system diagnostic purposes. class b module outputs transceiver output (bus) this is the output driver stage that sources current to the bus. its output follows the waveshaped waveform input. its output voltage is limited to 6.25 v to 8.0 v under normal battery level conditions. the limited level is controlled by an internal regulator/clamp circuit. once the battery voltage drops below 9.0 v, the regulator / clamp circuit saturates, causing the bus voltage to track the battery voltage. a 1.5 k ? 5% external resistor (as well as any 10.6 k ? pull-down resistors of any secondary nodes) sinks the current to discharge the capacitors during high-to-low transitions. this sourcing output is short circuit-protected (60 ma to 170 ma) against a short to -2.0 v and sinks less than 1.0 ma when shorted to v bat . if a short occurs, the overtemperature shutdown circuit protects the source driver of the device. in the event battery power is lost to the assembly, the bus transmitter's output stage will be disabled and the leakage current from the bus output will not source or sink more than 100 ma of current. the transceiver will operate with a remote ground offset of 2.0 v, but the lower corners of transmission will not be rounded during this condition. receiver output to the microcontroller (rx) this is a 5.0 v cmos compatible push-pull output used to send received data to the microcontroller. it does not require an external pull-up resistor to be used. the receiver is always enabled and draws less than 65 a of current from v bat . the receive threshold is dependent on the state of the sleep pin. the initial state of this output is always a logic [0] after supply voltage is applied, but before the sleep pin goes to a logic [1] state. the receiver circuitry is able to operate with v bat voltages as low as 4.25 v and still remains capable of ?waking up? the 33990 when remote class b activity is detected. when the sleep pin is low and message activity occurs on the bus, the receiver passes the bus message through to the microcontroller. the 33990 does not automatically ?wake up? from a sleep state when bus activity occurs: the microcontroller must tell it to do so. in the static electrical characteristics table, the maximum voltage for rx is specified as 4.75 v over an operating range of -40 c to 125 c temperature and 7.0 v to 16 v v bat . this maximum rx voltage is compatible with the minimum v dd voltage of microcontrollers to prevent the 33990 from sourcing current to the microcontroller's output. switched ground output (load) normally this output is a saturated switch to ground, which pulls down the external resistor between the bus and load outputs. in the event ground is lost to the assembly, the load output will bias itself ?off? and will not leak more than 100 a of current out of this pin. overtemperature shutdown if the bus output becomes shorted to ground for any duration, an overtemperature shutdown circuit ?latches off? the output source transistor whenever the die temperature exceeds 150 c to 190 c. the output transistor remains latched off until the tx input is toggled from a logic [0] to a logic [1]. the rising edge provides the clearing function, provided the locally sensed temperature is 10 c to 15 c below the latch-off temperature trip temperature. waveshaping waveshaping is incorporated into the 33990 to minimize radiated emi emissions. receiver protocol the class b communication scheme uses a variable pulse width (vpw) protocol. the microcontroller provides the vpw decoding function. once the receiver detects a transition on rx, it starts an internal counter. the initial ?start of frame? bit is a logic [1] and lasts 200 s. for subsequent bits, if there is a bus
analog integrated circuit device data freescale semiconductor 13 33990 typical applications functional pin description transition before 96 s, one logic state is inferred. if there is a bus transition after 96 s, the other logic state is inferred. the ?end of data? bit is a logic [0] and lasts 200 s. if there is no activity on the bus for 280 s to 320 s following a broadcast message, multiple unit nodes may arbitrate for control of the next message. during an arbitration, after the ?start of frame? bit has been transmitted, the secondary node transmitting the most consecutive logic [0] bits will be granted sole transmission access to the bus for that message. loss of assembly ground connection the definition of a loss of assembly ground condition at the device level is that all pins of the 33990, with the exception of bus and load, see a very low impedance to v bat . the load pin of the device has an internal transistor switch connected to it that is normally saturated to ground. this pulls the load-side of the external resistor (tied from bus to load) to ground under normal conditions. the load pin switch is essentially that of an ?upside down? fet, which is normally biased ?on? so long as module ground is present and biased ?off? when loss-of-ground occurs. when a loss of assembly ground occurs, the load transistor switch is self- biased ?off?, allowing no more than 100 a of leakage current to flow in the load pin. during such a loss of assembly ground condition, the bus and load pins exhibit a high impedance to v bat ; all other pins will exhibit a low impedance to v bat . during this condition the bus pin is prevented from sourcing any current or loading the bus, which would cause a corruption of any data being transmitted on the bus. while a particular assembly is experiencing a loss of ground, all other assembly nodes are permitted to function normally. it should be noted that with other nodes existing on the bus, the bus will always have some minimum / maximum impedance to ground as shown in table 6 , page 11 . loss of assembly battery connection the definition of a loss of assembly battery condition at the device level is that the v bat pin of the 33990 sees an infinite impedance to v bat , but there is some undefined impedance between these pins and ground. figure 14. typical application bus +vbat sleep tx rx 4x/loop gnd load primary node mcu v bat secondary nodes 33990 10.6 k ? 470pf 47 h
analog integrated circuit device data 14 freescale semiconductor 33990 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. d suffix ef suffix (pb-free) 8-pin plastic package 98asb42564b
analog integrated circuit device data freescale semiconductor 15 33990 revision history revision history revision date description of changes 2.0 10/2006 ? implemented revision history page ? converted to freescale format 3.0 11 /2006 ? removed peak package reflow temperature du ring reflow (solder reflow) parameter from maximum ratings on page 4 . added note with instructions to obtain this information from www.freescale.com .
mc33990 rev 3.0 11/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for furt her informa tion, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s envi ronmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate ta i p o , n . t. , h o n g k o n g +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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